globl mem_ctrl_asm_init一

.globl mem_ctrl_asm_init

mem_ctrl_asm_init:

/* s5pc100 使用的的dram芯片为k4t1g164qf-bce7 */

ldr r0, =0xe6000000 /*APB_DMC_BASE*/

/******************** DLL initialization **************************/

/* dll延时锁相环 使能dll*/
        /* 2. PhyControl0.ctrl_start_point andPhyControl0.ctrl_inc
&nnbsp;       * Set the PhyControl0.ctrl_dll_onbit-field to 1 to turn on the PHY DLL
        */

ldr r1, =0x50101002
        str r1, [r0, #0x18] /*PHY control 0 register*/

/*3.Set the PhyControl1.ctrl_shiftc andPhyControl1.ctrl_offsetc */
        ldr r1, =0xf6 /* step 3 0x110 when DDR2*/
        str r1, [r0, #0x1c] /*PHY control 1 register*/

ldr r1, =0x00000000
        str r1, [r0, #0x20] /*PHY control 2 register*/

/* 4. Set the PhyControl0.ctrl_start bit-field to 1 */
        ldr r1, =0x50101003
        str r1, [r0, #0x18] /*PHY control 0 register*/

/************************** DLL initialization - END ************************/

/* 5. Set the ConControl. At this moment, an auto refresh counter should be off.*/
        ldr r1, =0xFF001010
        str r1, [r0, #0x0] /*e6000000 = controller control register*/

ldr r1, =( (2<<20)|(1<<16)|(2<<12)|(4<<8) )
        /* 0x202400 DDR2 ,mem_width=32,2 chips,Memory Burst Length =4 */
        str r1, [r0, #0x4]
        /*e6000004 = memory control register*/

@ 128MB config , 8banks , linear, Row=13bit,COL=10bit
        @ldr r1, =0x20F01313
        ldr r1, =0x20e00313
        str r1, [r0, #0x8]

@ldr r1, =0x40F01313
        ldr r1, =0x30e00323
        str r1, [r0, #0xc]

ldr r1, =0x20000000
        str r1, [r0, #0x14] /*precharge policy configuration register*/

@ldr r1, =0x00100004
        @str r1, [r0, #0x28] /*precharge policy configuration register*/

/******************************************************************/

@ldr r1, =0x0000050e
        ldr r1, =0x00000400
        str r1, [r0, #0x30] /*AC timing register for auto refresh of memory*/

@ldr r1, =0x16233297 @TimingRow @166MHz
        ldr r1, =0x16233287
        str r1, [r0, #0x34] /*AC timing register for the row of memory*/

@; ldr r1, =0x24250304 @CL=5
        @ldr r1, =0x23230000 @CL=3
        ldr r1, =0x23240304
        str r1, [r0, #0x38] /*AC timing register for the data of memory*/

@ldr r1, =0x07c80232 @Timing Power
        ldr r1, =0x09c80232
        str r1, [r0, #0x3c] /*AC timing register for the power mode of memory*/

/************************ direct command for DDR2 ***********************/

ldr r1, =0x07000000 @chip0 Deselect
        str r1, [r0, #0x10] /*memory direct command register*/

ldr r1, =0x01000000 @chip0 PALL
        str r1, [r0, #0x10]

ldr r1, =0x00020000 @chip0 EMRS2
        str r1, [r0, #0x10]

ldr r1, =0x00030000 @chip0 EMRS3
        str r1, [r0, #0x10]

ldr r1, =0x00010400 @chip0 EMRS1 (MEM DLL on = DQS# disable)
        str r1, [r0, #0x10]

@; ldr r1, =0x00000552 @chip0 MRS (MEM DLL reset) CL=5, Burst Length=4
        ldr r1, =0x00000542 @chip0 MRS (MEM DLL reset) CL=3, Burst Length=4
        str r1, [r0, #0x10]

ldr r1, =0x01000000 @chip0 PALL
        str r1, [r0, #0x10]

ldr r1, =0x05000000 @chip0 REFA
        str r1, [r0, #0x10

ldr r1, =0x05000000 @chip0 REFA
        str r1, [r0, #0x10]

@; ldr r1, =0x00000452 @chip0 MRS (MEM DLL unreset) , BL=4 , CL=5
        strldr r1, =0x00000442 @chip0 MRS (MEM DLL unreset) , BL=4 , CL=3
        strstr r1, [r0, #0x10]

ldr r1, =0x00010780 @chip0 EMRS1 (OCD default)
        str r1, [r0, #0x10]

ldr r1, =0x00010400 @chip0 EMRS1 (OCD exit) Reduced Strength
        str r1, [r0, #0x10]

/************************ direct command for DDR2 - END*******************/

@ldr r1, =0x00FF20B0 @ConControl auto refresh on
        ldr r1, =0xff01030
        str r1, [r0, #0x0] /*e6000000 = controller control register*/

ldr r1, =0x00100004
        str r1, [r0, #0x28]

@ldr r1, =0x00212413 @ MemControl
        ldr r1, =0x00202400
        str r1, [r0, #0x4] /*e6000000 = controller control register*/